uart verilog by alexforencich
M1-M3 candidateCommon GitHub UART implementation.
githubAuto indexedunknown
The license requires manual review.
/cores
Core comparison
Comparison helps you see quickly which core carries less license, review, and integration risk.
Decision matrix
How to read the matrixStart with review status, license clarity, and warnings. If records are close, then look at tests, board evidence, and toolchain fit.2/4AccelFury core-template
M2-M3 templateШаблон production-style FPGA IP: manifest, registry, board/toolchain scaffolding, SPDX checks, separated licenses and release checklist.
githubManually reviewedCERN-OHL-S-2.0 + AGPL + CC-BY-SA
This is a template/example, not a standalone core.
Generated projects require separate review.
| Signal | uart verilog by alexforencich | AccelFury core-template |
|---|---|---|
| Category / source | peripheral/UART github | generator / template / IP methodology github |
| Review / maturity | Auto indexed M1-M3 candidate | Manually reviewed M2-M3 template |
| License | unknownUnknown | CERN-OHL-S-2.0 + AGPL + CC-BY-SAManual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: NoCI: NoFormal: No | Tests: NoCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: NoFuseSoC: NoBoard demo: No | Docs: YesFuseSoC: NoBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | UARTunknown | unknownunknown |
| Toolchains | Verilator | Verilator |
| Warnings |
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