troubleshootingbeginnerconfidence 4/5CC BY 4.0

Common beginner FPGA mistakes

Most beginner failures come from missing constraints, misunderstood clocks, latch inference, multiple drivers, skipped simulation and wrong board variant.

Debug from the board outward: known-good example, clock, reset, constraints, top-level ports, simple simulation, synthesis warnings, timing report, programming log. Treat warnings as design evidence, not noise.

Graph links

Boards: none

Chips: none

Toolchains: vivado-webpack, quartus-prime, gowin-eda, yosys

Protocols: none

Pitfalls: Thinking delay statements synthesize into hardware delays. Using blocking/nonblocking assignments without a consistent rule. Assuming simulation and hardware are equivalent without reset and timing checks.

Sources

https://yosyshq.readthedocs.io/projects/yosys/en/latest/https://verilator.org/guide/latest/

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