Open-source educational Lattice iCE40UP5K board designed around the Yosys, nextpnr and IceStorm flow.
iCE40UP5K-SG48open toolchainprice unknowneducationcontroldspformal
Enter board slugs separated by commas, for example: sipeed/tang-nano-20k,icebreaker/icebreaker.
Open-source educational Lattice iCE40UP5K board designed around the Yosys, nextpnr and IceStorm flow.
Terasic MAX 10 educational board for Intel FPGA introductory labs.
| Field | iCEBreaker | DE10-Lite |
|---|---|---|
| Chip | iCE40UP5K-SG48 | 10M50DAF484C7G |
| Family | iCE40 UltraPlus | MAX 10 |
| Device type | FPGA | FPGA |
| Price | unknown | unknown |
| Toolchains | Yosys + nextpnr + IceStorm, Lattice Diamond Programmer | Intel Quartus Prime |
| Open toolchain | yes | no |
| Interfaces | microUSB FT2232H, FT2232H programming, USB serial | VGA, USB-Blaster |
| Memory | QSPI flash 128 Mbit | SDRAM requires Terasic manual verification |
| Documentation | 82 | 75 |
| Difficulty | beginner | beginner |
| Openness score | 96 | 10 |
| Where to get help | iCEBreaker community docs | Terasic support |
| Typical risks | Check add-on pinout and exact hardware revision before connecting Pmods. | MAX 10 is not a Linux-on-FPGA target; use for digital logic and peripheral labs. |
| Better for | open-source flow | beginner learning |