FPGA from zero
D1beginner
Concepts, first HDL, simulation and waveform reading.
edu.fpga.camp
edu.fpga.camp v1
Roadmap, diagnostic, HDL Practice Lab, waveform, constraints, boards, projects and educator kits.
Embedded/software to FPGA
D2embeddedsoftware
Translate sequential programming habits into clocked hardware thinking.
Verilog fundamentals
D2studentjunior
Verilog combinational and sequential exercises with deterministic tests.
VHDL fundamentals
D2studentjunior
VHDL entity, process, numeric_std and simulation basics.
Simulation and verification basics
D2studentjunior
Debug with testbenches, logs and waveforms before touching a board.
Constraints and timing basics
D3juniormiddle
Clock constraints, port matching, setup/hold/slack and safe limitations.
Open-source FPGA flow
D3open-sourcejunior
Icarus, GHDL, Verilator and curated Yosys examples without vendor cloud tools.
Educator lab path
D2educator
Ready labs, rubrics and course plans for 4/8/12 week classes.
Start diagnostic
Placement test maps role to skills, lessons and tasks.
HDL Practice Lab
75 seeded tasks with deterministic profiles.
Educator toolkit
Read-only v1 labs, rubrics and course plans.