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Real Intent

Real Intent develops static RTL checks for FPGA and ASIC signoff.

Company website: realintent.com

Results

  • The release describes reset-tree and X-source analysis for FPGA and SoC signoff.

    Source: realintent.comChecked

Materials and products

Materials: 2

Overview

Its tools cover lint, clock-domain crossings, reset-domain crossings and reset/X analysis.

Verified activity