Primary risk

How to read riskThe risk banner compresses license clarity and review state into a short verdict. Integration decisions still need tests, synthesis, and board evidence.
There are blocking license or reuse risksA separate commercial license may be required.
Source-available limitationManually reviewed

Warnings

4
Critical

Source is available, but commercial use may require a separate license.

Info

The core does not include a decimator/CIC/FIR pipeline.

Warning

Confirmed board evidence with a real microphone is still missing.

Warning

Check clock/reset handling and constraints before integration.

Purpose and boundaries

Raw PDM RX core на Verilog-2001 для MEMS microphones: генерирует PDM clock, сэмплирует 1-битный поток и выдаёт valid/ready stream. Не выполняет PDM-to-PCM decimation.

Core kind and readiness

Readiness focusIf the status is not yet reproduced, close license, tests, and board-level evidence gaps first. The fields below are for quick scope checking.
Core kind
audioVerilog-2001
Interfaces / buses / flow
PDMVerilator

Still missing before production

2
  • No reproducible tests or CI smoke are confirmed yet.
  • Documentation does not yet look sufficient for quick integration.

Scores

What scores meanEach scale is independent. High usefulness does not cancel a license blocker, and high confidence does not replace board evidence.
Quality48
Usefulness72
Integration49
Verification37
Docs40
License42
Beginner42
Professional68
RAG55
Confidence20

Engineering signals

Signals legendSignals show whether useful engineering artefacts are visible. "Yes" does not imply completeness, and "No" often means missing evidence rather than impossible support.
TestsTests: current metadata says No.
CICI: current metadata says No.
FormalFormal: current metadata says No.
DocsDocs: current metadata says No.
FuseSoCFuseSoC: current metadata says No.
Board demoBoard demo: current metadata says Yes.
Open flowOpen flow: current metadata says No.
CommercialCommercial: current metadata says Review.

License matrix

Why split by scopeHDL, docs, tests, and generated artifacts can carry different terms. Commercial use is split out so each card does not repeat the same prose.
HDLAccelFury Source Available
DocumentationAccelFury Source Available
TestsUnknown
ExamplesUnknown
ArtifactsUnknown
Commercial useManual review required

Board compatibility

BoardStatusEvidence statusToolchain
Tang Primer 20K DockSynthesized for targetbuild/program evidence exists; microphone measurement pendingGowin/Yosys-nextpnr-apicula review
Tang Nano 20KLikely compatiblesame Gowin resource class; board constraints and real MEMS microphone test requiredGowin/Yosys-nextpnr-apicula review

Evidence matrix

How to read evidenceEach group only shows confirmed links. The confidence floor is a lower trust bound, not an absolute verdict.

Local verification

1
  • Try a synthesis smoke run with: Verilator.

Links and alternatives