Generators and frameworks

3 cores. Check the license and tests before integration.

AccelFury core-template

Checked on GitHub

FPGA IP template with a manifest, board and toolchain configuration, SPDX checks, separate licenses and a release checklist.

Generators and frameworksRust/SystemVerilog/TypeScriptCERN-OHL-S-2.0 + AGPL + CC-BY-SAM2 · Simulation-testedupdated 5 months ago

Checked on GitHub

Central open SoC builder and integration framework.

Generators and frameworksMigen/Python/VerilogNo license foundM4 · Production-readyupdated 3 days ago

Modern Python-based HDL ecosystem source.

Generators and frameworksNo license foundM1 · Prototype