Wishbone/AXI bridge and formal property library.
Buses and infrastructureVerilogNo license foundM1 · Prototype
Buses and infrastructure
14 cores. Check the license and tests before integration.
FuseSoC-listed open logic package family.
Buses and infrastructureNo license foundM1 · Prototype
AXI components and infrastructure.
Buses and infrastructureSystemVerilogNo license foundM1 · Prototype
Common Wishbone interconnect package.
Buses and infrastructureNo license foundM1 · Prototype
CDC helpers for composition planner.
Buses and infrastructureNo license foundM1 · Prototype
Reusable cells widely used by PULP projects.
Buses and infrastructureSystemVerilogNo license foundM1 · Prototype
Stream FIFO/width conversion baseline.
Buses and infrastructureNo license foundM1 · Prototype
Successor ecosystem for AXI/stream components.
Buses and infrastructureNo license foundM1 · Prototype
AXI component library and comparison source.
Buses and infrastructureNo license foundM1 · Prototype
AXI-Stream component library.
Buses and infrastructureNo license foundM1 · Prototype
GPIO reference with register docs.
Buses and infrastructureNo license foundM0 · Idea
Reusable SystemVerilog library.
Buses and infrastructureNo license foundM1 · Prototype
Primitive library reference.
Buses and infrastructureNo license foundM0 · Idea
GPIO category seed.
Buses and infrastructureVerilog/VHDL unknown until reviewNo license foundM1 · Prototype