LiteDRAM
Checked on GitHubOpen DRAM controller ecosystem used with LiteX.
Memory and storageMigen/Python/VerilogNo license foundM2 · Simulation-testedupdated 3 days ago
Memory and storage
9 cores. Check the license and tests before integration.
LiteSATA
Checked on GitHubHigh-value storage/networked design reference.
Memory and storageMigen/Python/VerilogNo license foundM2 · Simulation-testedupdated 3 days ago
LiteSDCard
Checked on GitHubUseful storage peripheral for SoC designs.
Memory and storageMigen/Python/VerilogNo license foundM2 · Simulation-testedupdated 3 days ago
Minimal SoC building block.
Memory and storageNo license foundM1 · Prototype
Generic FIFO baseline.
Memory and storageNo license foundM1 · Prototype
Open cache candidate.
Memory and storageNo license foundM1 · Prototype
HyperRAM/HyperFlash ecosystem core.
Memory and storageNo license foundM1 · Prototype
DDR risk-model example.
Memory and storageVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
Memory controller comparison.
Memory and storageVerilog/VHDL unknown until reviewNo license foundM1 · Prototype