Example of DSP cores with Wishbone and claimed FPGA evidence.
DSP and radioVHDLLGPLM1 · Prototype
DSP and radio
4 cores. Check the license and tests before integration.
JESD204B open core candidate.
DSP and radioNo license foundM1 · Prototype
CORDIC category seed.
DSP and radioVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
FFT category seed.
DSP and radioVerilog/VHDL unknown until reviewNo license foundM1 · Prototype