BaseJump STL
unknownReusable SystemVerilog library.
githubUnreviewedunknown
The license requires manual review.
Comparison helps you see quickly which core carries less license, review, and integration risk.
Reusable SystemVerilog library.
The license requires manual review.
High-quality IP block library with docs and verification culture.
Manual review is required.
| Signal | BaseJump STL | OpenTitan IP blocks |
|---|---|---|
| Category / source | library/SystemVerilog github | security/root-of-trust/IP blocks github |
| Review / maturity | Unreviewed unknown | Auto indexed M1-M3 candidate |
| License | unknownUnknown | Apache-2.0Manual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: NoCI: NoFormal: No | Tests: YesCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: NoFuseSoC: NoBoard demo: No | Docs: NoFuseSoC: NoBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | unknownunknown | unknownunknown |
| Toolchains | Verilator | Verilator |
| Warnings |
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