FPGA Interchange
M0-M2Toolchain interoperability source.
githubUnreviewedunknown
The license requires manual review.
This is not confirmed to be a reusable RTL core.
Comparison helps you see quickly which core carries less license, review, and integration risk.
Toolchain interoperability source.
The license requires manual review.
This is not confirmed to be a reusable RTL core.
Bus protocol reference for OpenCores-era reusable IP.
Manual review is required.
| Signal | FPGA Interchange | OpenCores Wishbone |
|---|---|---|
| Category / source | tooling/interchange github | bus/Wishbone opencores |
| Review / maturity | Unreviewed M0-M2 | Auto indexed M6 |
| License | unknownUnknown | public-domain-like per OpenCores WISHBONE pageManual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: NoCI: NoFormal: No | Tests: NoCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: NoFuseSoC: NoBoard demo: No | Docs: YesFuseSoC: NoBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | unknownunknown | unknownWishbone |
| Toolchains | unknown | unknown |
| Warnings |
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