hdl-util VGA
unknownVGA timing core candidate.
githubUnreviewedunknown
The license requires manual review.
Comparison helps you see quickly which core carries less license, review, and integration risk.
VGA timing core candidate.
The license requires manual review.
Bus protocol reference for OpenCores-era reusable IP.
Manual review is required.
| Signal | hdl-util VGA | OpenCores Wishbone |
|---|---|---|
| Category / source | video/VGA github | bus/Wishbone opencores |
| Review / maturity | Unreviewed unknown | Auto indexed M6 |
| License | unknownUnknown | public-domain-like per OpenCores WISHBONE pageManual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: NoCI: NoFormal: No | Tests: NoCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: NoFuseSoC: NoBoard demo: No | Docs: YesFuseSoC: NoBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | VGA/HDMIunknown | unknownWishbone |
| Toolchains | unknown | unknown |
| Warnings |
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