IObundle cache
M1-M3 candidateOpen cache candidate.
githubAuto indexedunknown
The license requires manual review.
Comparison helps you see quickly which core carries less license, review, and integration risk.
Open cache candidate.
The license requires manual review.
Industrial-grade open RISC-V core family source.
Manual review is required.
| Signal | IObundle cache | OpenHW CORE-V cores |
|---|---|---|
| Category / source | memory/cache github | processor/RISC-V github |
| Review / maturity | Auto indexed M1-M3 candidate | Auto indexed M1-M3 candidate |
| License | unknownUnknown | SolderpadManual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: NoCI: NoFormal: No | Tests: NoCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: NoFuseSoC: NoBoard demo: No | Docs: NoFuseSoC: NoBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | Memoryunknown | unknownunknown |
| Toolchains | unknown | Verilator |
| Warnings |
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