IObundle UART16550
M1-M3 candidateModern adaptation of OpenCores UART16550.
githubAuto indexedunknown
The license requires manual review.
Comparison helps you see quickly which core carries less license, review, and integration risk.
Modern adaptation of OpenCores UART16550.
The license requires manual review.
Bus protocol reference for OpenCores-era reusable IP.
Manual review is required.
| Signal | IObundle UART16550 | OpenCores Wishbone |
|---|---|---|
| Category / source | peripheral/UART github | bus/Wishbone opencores |
| Review / maturity | Auto indexed M1-M3 candidate | Auto indexed M6 |
| License | unknownUnknown | public-domain-like per OpenCores WISHBONE pageManual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: NoCI: NoFormal: No | Tests: NoCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: NoFuseSoC: NoBoard demo: No | Docs: YesFuseSoC: NoBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | UARTunknown | unknownWishbone |
| Toolchains | unknown | unknown |
| Warnings |
|
|