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Up to four cores side by side: maturity, license, tests and activity.

AttributeLiteSPIverilog-i2c
MaturityM2 · Simulation-testedM2 · Simulation-tested
LicenseBSD-2-Clause · Commercial-friendlyMIT · Commercial-friendly
LanguageMigen/Python/Verilog—
Testsyesyes
CIyes—
Formal——
FuseSoC——
Activityupdated 8 days agoupdated 2 years ago
Boards——
InterfacesSPI/QSPII2C
CategoryInterfaces and peripheralsInterfaces and peripherals

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