LiteX
M6Central open SoC builder and integration framework.
githubAuto indexedBSD-2-Clause-like until checked
Manual review is required.
Comparison helps you see quickly which core carries less license, review, and integration risk.
Central open SoC builder and integration framework.
Manual review is required.
Industrial-grade open RISC-V core family source.
Manual review is required.
| Signal | LiteX | OpenHW CORE-V cores |
|---|---|---|
| Category / source | SoC builder/generator github | processor/RISC-V github |
| Review / maturity | Auto indexed M6 | Auto indexed M1-M3 candidate |
| License | BSD-2-Clause-like until checkedManual review required | SolderpadManual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: NoCI: NoFormal: No | Tests: NoCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: NoFuseSoC: NoBoard demo: No | Docs: NoFuseSoC: NoBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | Memoryunknown | unknownunknown |
| Toolchains | LiteX, Verilator | Verilator |
| Warnings |
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