opencores minsoc
unknownHistorical SoC integration reference.
opencoresUnreviewedunknown
The license requires manual review.
The source appears stale or legacy.
Comparison helps you see quickly which core carries less license, review, and integration risk.
Historical SoC integration reference.
The license requires manual review.
The source appears stale or legacy.
Industrial-grade open RISC-V core family source.
Manual review is required.
| Signal | opencores minsoc | OpenHW CORE-V cores |
|---|---|---|
| Category / source | SoC/OpenRISC opencores | processor/RISC-V github |
| Review / maturity | Unreviewed unknown | Auto indexed M1-M3 candidate |
| License | unknownUnknown | SolderpadManual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: NoCI: NoFormal: No | Tests: NoCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: YesFuseSoC: NoBoard demo: No | Docs: NoFuseSoC: NoBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | unknownunknown | unknownunknown |
| Toolchains | unknown | Verilator |
| Warnings |
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