OpenCores WDSP
M1-M3 candidateExample of DSP cores with Wishbone and claimed FPGA evidence.
opencoresAuto indexedLGPL
The source appears stale or legacy.
/cores
Core comparison
Comparison helps you see quickly which core carries less license, review, and integration risk.
Decision matrix
How to read the matrixStart with review status, license clarity, and warnings. If records are close, then look at tests, board evidence, and toolchain fit.2/4AccelFury core-template
M2-M3 templateШаблон production-style FPGA IP: manifest, registry, board/toolchain scaffolding, SPDX checks, separated licenses and release checklist.
githubManually reviewedCERN-OHL-S-2.0 + AGPL + CC-BY-SA
This is a template/example, not a standalone core.
Generated projects require separate review.
| Signal | OpenCores WDSP | AccelFury core-template |
|---|---|---|
| Category / source | DSP/FIR/IIR/FFT opencores | generator / template / IP methodology github |
| Review / maturity | Auto indexed M1-M3 candidate | Manually reviewed M2-M3 template |
| License | LGPLManual review required | CERN-OHL-S-2.0 + AGPL + CC-BY-SAManual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: NoCI: NoFormal: No | Tests: NoCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: NoFuseSoC: NoBoard demo: No | Docs: YesFuseSoC: NoBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | unknownWishbone | unknownunknown |
| Toolchains | GHDL | Verilator |
| Warnings |
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