Decision matrix

How to read the matrixStart with review status, license clarity, and warnings. If records are close, then look at tests, board evidence, and toolchain fit.2/4

OpenCores WDSP

M1-M3 candidateMaturity levelMaturity M1-M3 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.

Example of DSP cores with Wishbone and claimed FPGA evidence.

opencoresAuto indexedLGPL
High

The source appears stale or legacy.

AccelFury core-template

M2-M3 templateMaturity levelMaturity M2-M3 template: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.

Шаблон production-style FPGA IP: manifest, registry, board/toolchain scaffolding, SPDX checks, separated licenses and release checklist.

githubManually reviewedCERN-OHL-S-2.0 + AGPL + CC-BY-SA
Info

This is a template/example, not a standalone core.

Info

Generated projects require separate review.

SignalOpenCores WDSPAccelFury core-template
Category / sourceDSP/FIR/IIR/FFT
opencores
generator / template / IP methodology
github
Review / maturity
Auto indexedM1-M3 candidateMaturity levelMaturity M1-M3 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Manually reviewedM2-M3 templateMaturity levelMaturity M2-M3 template: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
License
LGPLunknown_or_manual_review_required
CERN-OHL-S-2.0 + AGPL + CC-BY-SAunknown_or_manual_review_required
Evidence / boards
EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees.
EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees.
Board status
unknown
unknown
Tests / CI / formal
TestsCurrent metadata does not show reproducible test evidence yet.CICurrent metadata does not show confirmed CI yet.FormalFormal evidence has not been found yet.
TestsCurrent metadata does not show reproducible test evidence yet.CICurrent metadata does not show confirmed CI yet.FormalFormal evidence has not been found yet.
Docs / FuseSoC / board demo
DocsDocumentation is not evidence-confirmed yet.FuseSoCFuseSoC packaging has not been found yet.Board demoBoard-level demo or target evidence is not confirmed yet.
DocsDocumentation is visible in current metadata.FuseSoCFuseSoC packaging has not been found yet.Board demoBoard-level demo or target evidence is not confirmed yet.
Signals
QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification
QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification
Interfaces / buses
unknownWishbone
unknownunknown
ToolchainsGHDLVerilator
Warnings
  • The source appears stale or legacy.
  • This is a template/example, not a standalone core.
  • Generated projects require separate review.