OpenCores WDSP
M1-M3 candidateExample of DSP cores with Wishbone and claimed FPGA evidence.
opencoresAuto indexedLGPL
The source appears stale or legacy.
/cores
Core comparison
Comparison helps you see quickly which core carries less license, review, and integration risk.
Decision matrix
How to read the matrixStart with review status, license clarity, and warnings. If records are close, then look at tests, board evidence, and toolchain fit.2/4LiteX
M6Central open SoC builder and integration framework.
githubAuto indexedBSD-2-Clause-like until checked
Manual review is required.
| Signal | OpenCores WDSP | LiteX |
|---|---|---|
| Category / source | DSP/FIR/IIR/FFT opencores | SoC builder/generator github |
| Review / maturity | Auto indexed M1-M3 candidate | Auto indexed M6 |
| License | LGPLManual review required | BSD-2-Clause-like until checkedManual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: NoCI: NoFormal: No | Tests: NoCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: NoFuseSoC: NoBoard demo: No | Docs: NoFuseSoC: NoBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | unknownWishbone | Memoryunknown |
| Toolchains | GHDL | LiteX, Verilator |
| Warnings |
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