OpenCores WDSP
M1-M3 candidateExample of DSP cores with Wishbone and claimed FPGA evidence.
opencoresAuto indexedLGPL
The source appears stale or legacy.
Comparison helps you see quickly which core carries less license, review, and integration risk.
Example of DSP cores with Wishbone and claimed FPGA evidence.
The source appears stale or legacy.
Canonical UART reference and common FuseSoC adaptations.
The license requires manual review.
The source appears stale or legacy.
| Signal | OpenCores WDSP | OpenCores UART16550 |
|---|---|---|
| Category / source | DSP/FIR/IIR/FFT opencores | peripheral/UART opencores |
| Review / maturity | Auto indexed M1-M3 candidate | Auto indexed M1-M3 candidate |
| License | LGPLManual review required | unknown until checkedManual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: NoCI: NoFormal: No | Tests: NoCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: NoFuseSoC: NoBoard demo: No | Docs: YesFuseSoC: YesBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | unknownWishbone | UARTunknown |
| Toolchains | GHDL | FuseSoC, Verilator |
| Warnings |
|
|