The license requires manual review.
P0M1-M3 candidateMaturity levelMaturity M1-M3 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.Auto indexedopencores
OpenCores UART16550
Canonical UART reference and common FuseSoC adaptations.
Primary risk
How to read riskThe risk banner compresses license clarity and review state into a short verdict. Integration decisions still need tests, synthesis, and board evidence.Engineering review is still required before integrationHDL/docs/tests/examples still need manual review.
License needs reviewAuto indexed
Warnings
2The source appears stale or legacy.
Purpose and boundaries
Canonical UART reference and common FuseSoC adaptations.
Core kind and readiness
Readiness focusIf the status is not yet reproduced, close license, tests, and board-level evidence gaps first. The fields below are for quick scope checking.Core kind
peripheralVerilog
Interfaces / buses / flow
UARTFuseSoCVerilator
Still missing before production
3- A manual reviewer pass is still needed beyond seed metadata.
- No reproducible tests or CI smoke are confirmed yet.
- There is no board-level evidence with real constraints/report data yet.
Scores
What scores meanEach scale is independent. High usefulness does not cancel a license blocker, and high confidence does not replace board evidence.Quality48
Usefulness72
Integration76
Verification22
Docs62
License42
Beginner76
Professional68
RAG78
Confidence40
Engineering signals
Signals legendSignals show whether useful engineering artefacts are visible. "Yes" does not imply completeness, and "No" often means missing evidence rather than impossible support.TestsCurrent metadata does not show reproducible test evidence yet.
CICurrent metadata does not show confirmed CI yet.
FormalFormal evidence has not been found yet.
DocsDocumentation is visible in current metadata.
FuseSoCA FuseSoC .core file or compatible packaging is visible.
Board demoBoard-level demo or target evidence is not confirmed yet.
Open flowOpen-source FPGA flow compatibility is not confirmed yet.
CommercialCommercial use needs manual license review.
License matrix
Why split by scopeHDL, docs, tests, and generated artifacts can carry different terms. Commercial use is split out so each card does not repeat the same prose.HDLHDLunknown until checked: license value from current metadata.
DocumentationDocumentationUnknown: license evidence is missing for this scope.
TestsTestsUnknown: license evidence is missing for this scope.
ExamplesExamplesUnknown: license evidence is missing for this scope.
ArtifactsArtifactsUnknown: license evidence is missing for this scope.
Commercial useCommercial useunknown_or_manual_review_required: license value from current metadata.
Board compatibility
Compatibility is still unknownSynthesis/implementation evidence and reproducible board reports are still needed.
Evidence matrix
How to read evidenceEach group only shows confirmed links. The confidence floor is a lower trust bound, not an absolute verdict.Local verification
2- Inspect the upstream FuseSoC .core manifest and use it as the integration entrypoint.
- Try a synthesis smoke run with: FuseSoC, Verilator.