OpenCores WDSP
M1-M3 candidateExample of DSP cores with Wishbone and claimed FPGA evidence.
opencoresAuto indexedLGPL
The source appears stale or legacy.
Comparison helps you see quickly which core carries less license, review, and integration risk.
Example of DSP cores with Wishbone and claimed FPGA evidence.
The source appears stale or legacy.
Bus protocol reference for OpenCores-era reusable IP.
Manual review is required.
| Signal | OpenCores WDSP | OpenCores Wishbone |
|---|---|---|
| Category / source | DSP/FIR/IIR/FFT opencores | bus/Wishbone opencores |
| Review / maturity | Auto indexed M1-M3 candidate | Auto indexed M6 |
| License | LGPLManual review required | public-domain-like per OpenCores WISHBONE pageManual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: NoCI: NoFormal: No | Tests: NoCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: NoFuseSoC: NoBoard demo: No | Docs: YesFuseSoC: NoBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | unknownWishbone | unknownWishbone |
| Toolchains | GHDL | unknown |
| Warnings |
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