Bus protocol reference for OpenCores-era reusable IP.
opencoresAuto indexedpublic-domain-like per OpenCores WISHBONE page
Manual review is required.
Comparison helps you see quickly which core carries less license, review, and integration risk.
Bus protocol reference for OpenCores-era reusable IP.
Manual review is required.
Useful Wishbone-accessible debug core by ZipCPU author.
Manual review is required.
| Signal | OpenCores Wishbone | OpenCores WBScope |
|---|---|---|
| Category / source | bus/Wishbone opencores | verification/logic analyzer opencores |
| Review / maturity | Auto indexed M6 | Auto indexed M5 candidate |
| License | public-domain-like per OpenCores WISHBONE pageManual review required | GPLManual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: NoCI: NoFormal: No | Tests: NoCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: YesFuseSoC: NoBoard demo: No | Docs: NoFuseSoC: NoBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | unknownWishbone | JTAG/debugWishbone |
| Toolchains | unknown | Verilator |
| Warnings |
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