OpenHW CORE-V cores
M1-M3 candidateIndustrial-grade open RISC-V core family source.
githubAuto indexedSolderpad
Manual review is required.
Comparison helps you see quickly which core carries less license, review, and integration risk.
Industrial-grade open RISC-V core family source.
Manual review is required.
Central open SoC builder and integration framework.
Manual review is required.
| Signal | OpenHW CORE-V cores | LiteX |
|---|---|---|
| Category / source | processor/RISC-V github | SoC builder/generator github |
| Review / maturity | Auto indexed M1-M3 candidate | Auto indexed M6 |
| License | SolderpadManual review required | BSD-2-Clause-like until checkedManual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: NoCI: NoFormal: No | Tests: NoCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: NoFuseSoC: NoBoard demo: No | Docs: NoFuseSoC: NoBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | unknownunknown | Memoryunknown |
| Toolchains | Verilator | LiteX, Verilator |
| Warnings |
|
|