OpenRISC or1200
M1-M3 candidateHistorical open soft CPU baseline.
githubAuto indexedunknown
The license requires manual review.
Manual review is required.
Comparison helps you see quickly which core carries less license, review, and integration risk.
Historical open soft CPU baseline.
The license requires manual review.
Manual review is required.
Bus protocol reference for OpenCores-era reusable IP.
Manual review is required.
| Signal | OpenRISC or1200 | OpenCores Wishbone |
|---|---|---|
| Category / source | processor/OpenRISC github | bus/Wishbone opencores |
| Review / maturity | Auto indexed M1-M3 candidate | Auto indexed M6 |
| License | unknownUnknown | public-domain-like per OpenCores WISHBONE pageManual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: NoCI: NoFormal: No | Tests: NoCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: NoFuseSoC: NoBoard demo: No | Docs: YesFuseSoC: NoBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | unknownunknown | unknownWishbone |
| Toolchains | Verilator | unknown |
| Warnings |
|
|