Compare cores
Up to four cores side by side: maturity, license, tests and activity.
| Attribute | OpenTitan prim library | taxi | verilog-axis | wb_intercon |
|---|---|---|---|---|
| Maturity | M4 · Production-ready | M2 · Simulation-tested | M2 · Simulation-tested | M2 · Simulation-tested |
| License | Apache-2.0 · Commercial-friendly | CERN-OHL-S-2.0 · Copyleft | MIT · Commercial-friendly | ISC · Commercial-friendly |
| Language | — | — | — | — |
| Tests | yes | yes | yes | yes |
| CI | yes | yes | yes | — |
| Formal | yes | — | — | — |
| FuseSoC | yes | — | — | yes |
| Activity | updated 1 day ago | updated 35 days ago | updated 2 years ago | updated 7 months ago |
| Boards | — | — | — | — |
| Interfaces | — | FIFO/stream, AXI | FIFO/stream, AXI | Wishbone |
| Category | Buses and infrastructure | Buses and infrastructure | Buses and infrastructure | Buses and infrastructure |