Surelog
M0-M2SystemVerilog parsing support signal.
githubUnreviewedunknown
The license requires manual review.
This is not confirmed to be a reusable RTL core.
/cores
Core comparison
Comparison helps you see quickly which core carries less license, review, and integration risk.
Decision matrix
How to read the matrixStart with review status, license clarity, and warnings. If records are close, then look at tests, board evidence, and toolchain fit.2/4OpenCores WBScope
M5 candidateUseful Wishbone-accessible debug core by ZipCPU author.
opencoresAuto indexedGPL
Manual review is required.
| Signal | Surelog | OpenCores WBScope |
|---|---|---|
| Category / source | tooling/SystemVerilog parser github | verification/logic analyzer opencores |
| Review / maturity | Unreviewed M0-M2 | Auto indexed M5 candidate |
| License | unknownUnknown | GPLManual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: NoCI: NoFormal: No | Tests: NoCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: NoFuseSoC: NoBoard demo: No | Docs: NoFuseSoC: NoBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | unknownunknown | JTAG/debugWishbone |
| Toolchains | Verilator | Verilator |
| Warnings |
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