Surelog
M0-M2SystemVerilog parsing support signal.
githubUnreviewedunknown
The license requires manual review.
This is not confirmed to be a reusable RTL core.
Comparison helps you see quickly which core carries less license, review, and integration risk.
SystemVerilog parsing support signal.
The license requires manual review.
This is not confirmed to be a reusable RTL core.
High-quality IP block library with docs and verification culture.
Manual review is required.
| Signal | Surelog | OpenTitan IP blocks |
|---|---|---|
| Category / source | tooling/SystemVerilog parser github | security/root-of-trust/IP blocks github |
| Review / maturity | Unreviewed M0-M2 | Auto indexed M1-M3 candidate |
| License | unknownUnknown | Apache-2.0Manual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: NoCI: NoFormal: No | Tests: YesCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: NoFuseSoC: NoBoard demo: No | Docs: NoFuseSoC: NoBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | unknownunknown | unknownunknown |
| Toolchains | Verilator | Verilator |
| Warnings |
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