Compare cores

Up to four cores side by side: maturity, license, tests and activity.

Attributetaxistream_utilsverilog-axisverilog-axi
MaturityM2 · Simulation-testedM2 · Simulation-testedM2 · Simulation-testedM2 · Simulation-tested
LicenseCERN-OHL-S-2.0 · CopyleftISC · Commercial-friendlyMIT · Commercial-friendlyMIT · Commercial-friendly
Language————
Testsyesyesyesyes
CIyes—yesyes
Formal————
FuseSoC—yes——
Activityupdated 35 days agoupdated 12 months agoupdated 2 years agoupdated 2 years ago
Boards————
InterfacesFIFO/stream, AXIFIFO/streamFIFO/stream, AXIAXI
CategoryBuses and infrastructureBuses and infrastructureBuses and infrastructureBuses and infrastructure