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Up to four cores side by side: maturity, license, tests and activity.

Attributetaxiverilog-axistream_utils
MaturityM2 · Simulation-testedM2 · Simulation-testedM2 · Simulation-tested
LicenseCERN-OHL-S-2.0 · CopyleftMIT · Commercial-friendlyISC · Commercial-friendly
Language———
Testsyesyesyes
CIyesyes—
Formal———
FuseSoC——yes
Activityupdated 35 days agoupdated 2 years agoupdated 12 months ago
Boards———
InterfacesFIFO/stream, AXIAXIFIFO/stream
CategoryBuses and infrastructureBuses and infrastructureBuses and infrastructure

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