Compare cores

Up to four cores side by side: maturity, license, tests and activity.

Attributetaxiverilog-axisverilog-axistream_utils
MaturityM2 · Simulation-testedM2 · Simulation-testedM2 · Simulation-testedM2 · Simulation-tested
LicenseCERN-OHL-S-2.0 · CopyleftMIT · Commercial-friendlyMIT · Commercial-friendlyISC · Commercial-friendly
Language————
Testsyesyesyesyes
CIyesyesyes—
Formal————
FuseSoC———yes
Activityupdated 35 days agoupdated 2 years agoupdated 2 years agoupdated 12 months ago
Boards————
InterfacesFIFO/stream, AXIFIFO/stream, AXIAXIFIFO/stream
CategoryBuses and infrastructureBuses and infrastructureBuses and infrastructureBuses and infrastructure