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Up to four cores side by side: maturity, license, tests and activity.

Attributeverilog-axistream_utils
MaturityM2 · Simulation-testedM2 · Simulation-tested
LicenseMIT · Commercial-friendlyISC · Commercial-friendly
Language——
Testsyesyes
CIyes—
Formal——
FuseSoC—yes
Activityupdated 2 years agoupdated 12 months ago
Boards——
InterfacesAXIFIFO/stream
CategoryBuses and infrastructureBuses and infrastructure

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