Compare cores

Up to four cores side by side: maturity, license, tests and activity.

Attributeverilog-axistream_utilstaxiverilog-axis
MaturityM2 · Simulation-testedM2 · Simulation-testedM2 · Simulation-testedM2 · Simulation-tested
LicenseMIT · Commercial-friendlyISC · Commercial-friendlyCERN-OHL-S-2.0 · CopyleftMIT · Commercial-friendly
Language————
Testsyesyesyesyes
CIyes—yesyes
Formal————
FuseSoC—yes——
Activityupdated 2 years agoupdated 12 months agoupdated 35 days agoupdated 2 years ago
Boards————
InterfacesAXIFIFO/streamFIFO/stream, AXIFIFO/stream, AXI
CategoryBuses and infrastructureBuses and infrastructureBuses and infrastructureBuses and infrastructure