Compare cores

Up to four cores side by side: maturity, license, tests and activity.

Attributeverilog-axitaxistream_utilsverilog-axis
MaturityM2 · Simulation-testedM2 · Simulation-testedM2 · Simulation-testedM2 · Simulation-tested
LicenseMIT · Commercial-friendlyCERN-OHL-S-2.0 · CopyleftISC · Commercial-friendlyMIT · Commercial-friendly
Language————
Testsyesyesyesyes
CIyesyes—yes
Formal————
FuseSoC——yes—
Activityupdated 2 years agoupdated 35 days agoupdated 12 months agoupdated 2 years ago
Boards————
InterfacesAXIFIFO/stream, AXIFIFO/streamFIFO/stream, AXI
CategoryBuses and infrastructureBuses and infrastructureBuses and infrastructureBuses and infrastructure