Compare cores

Up to four cores side by side: maturity, license, tests and activity.

Attributeverilog-axiverilog-axisstream_utilstaxi
MaturityM2 · Simulation-testedM2 · Simulation-testedM2 · Simulation-testedM2 · Simulation-tested
LicenseMIT · Commercial-friendlyMIT · Commercial-friendlyISC · Commercial-friendlyCERN-OHL-S-2.0 · Copyleft
Language————
Testsyesyesyesyes
CIyesyes—yes
Formal————
FuseSoC——yes—
Activityupdated 2 years agoupdated 2 years agoupdated 12 months agoupdated 35 days ago
Boards————
InterfacesAXIFIFO/stream, AXIFIFO/streamFIFO/stream, AXI
CategoryBuses and infrastructureBuses and infrastructureBuses and infrastructureBuses and infrastructure