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Up to four cores side by side: maturity, license, tests and activity.

Attributeverilog-ethernetverilog-i2cOpenTitan SPI device IP
MaturityM2 · Simulation-testedM2 · Simulation-testedM4 · Production-ready
LicenseMIT · Commercial-friendlyMIT · Commercial-friendlyApache-2.0 · Commercial-friendly
Language———
Testsyesyesyes
CIyes—yes
Formal———
FuseSoC——yes
Activityupdated 2 years agoupdated 2 years agoupdated 1 day ago
Boards———
InterfacesEthernetI2CSPI/QSPI
CategoryInterfaces and peripheralsInterfaces and peripheralsInterfaces and peripherals

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