Comparison helps you see quickly which core carries less license, review, and integration risk.
PCIe endpoint/DMA candidate.
The license requires manual review.
There is a vendor tooling or license constraint.
Central open SoC builder and integration framework.
Manual review is required.
| Signal | verilog-pcie | LiteX |
|---|---|---|
| Category / source | peripheral/PCIe github | SoC builder/generator github |
| Review / maturity | UnreviewedunknownMaturity levelMaturity unknown: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale. | Auto indexedM6Maturity levelMaturity M6: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale. |
| License | unknownunknown_or_manual_review_required | BSD-2-Clause-like until checkedallowed_by_current_metadata |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | TestsCurrent metadata does not show reproducible test evidence yet.CICI or a similar automated check is visible in current metadata.FormalFormal evidence has not been found yet. | TestsCurrent metadata does not show reproducible test evidence yet.CICurrent metadata does not show confirmed CI yet.FormalFormal evidence has not been found yet. |
| Docs / FuseSoC / board demo | DocsDocumentation is not evidence-confirmed yet.FuseSoCFuseSoC packaging has not been found yet.Board demoBoard-level demo or target evidence is not confirmed yet. | DocsDocumentation is not evidence-confirmed yet.FuseSoCFuseSoC packaging has not been found yet.Board demoBoard-level demo or target evidence is not confirmed yet. |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | PCIeunknown | Memoryunknown |
| Toolchains | Verilator | LiteX, Verilator |
| Warnings |
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