verilog-pcie
unknownPCIe endpoint/DMA candidate.
githubUnreviewedunknown
The license requires manual review.
There is a vendor tooling or license constraint.
/cores
Core comparison
Comparison helps you see quickly which core carries less license, review, and integration risk.
Decision matrix
How to read the matrixStart with review status, license clarity, and warnings. If records are close, then look at tests, board evidence, and toolchain fit.2/4Bus protocol reference for OpenCores-era reusable IP.
opencoresAuto indexedpublic-domain-like per OpenCores WISHBONE page
Manual review is required.
| Signal | verilog-pcie | OpenCores Wishbone |
|---|---|---|
| Category / source | peripheral/PCIe github | bus/Wishbone opencores |
| Review / maturity | Unreviewed unknown | Auto indexed M6 |
| License | unknownUnknown | public-domain-like per OpenCores WISHBONE pageManual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: NoCI: YesFormal: No | Tests: NoCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: NoFuseSoC: NoBoard demo: No | Docs: YesFuseSoC: NoBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | PCIeunknown | unknownWishbone |
| Toolchains | Verilator | unknown |
| Warnings |
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