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Up to four cores side by side: maturity, license, tests and activity.

AttributeVexRiscvSERV
MaturityM2 · Simulation-testedM4 · Production-ready
LicenseMIT · Commercial-friendlyISC · Commercial-friendly
LanguageSpinalHDL/Scala/VerilogVerilog
Testsyesyes
CIyesyes
Formal——
FuseSoC—yes
Activityupdated 5 days agoupdated 38 days ago
Boards——
Interfaces——
CategoryCPUs and computeCPUs and compute

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