Compare cores
Up to four cores side by side: maturity, license, tests and activity.
| Attribute | wb_intercon | verilog-axis | OpenTitan prim library |
|---|---|---|---|
| Maturity | M2 · Simulation-tested | M2 · Simulation-tested | M4 · Production-ready |
| License | ISC · Commercial-friendly | MIT · Commercial-friendly | Apache-2.0 · Commercial-friendly |
| Language | — | — | — |
| Tests | yes | yes | yes |
| CI | — | yes | yes |
| Formal | — | — | yes |
| FuseSoC | yes | — | yes |
| Activity | updated 7 months ago | updated 2 years ago | updated 1 day ago |
| Boards | — | — | — |
| Interfaces | Wishbone | FIFO/stream, AXI | — |
| Category | Buses and infrastructure | Buses and infrastructure | Buses and infrastructure |