wb_ram
M1-M3 candidateMinimal SoC building block.
githubAuto indexedunknown
The license requires manual review.
Comparison helps you see quickly which core carries less license, review, and integration risk.
Minimal SoC building block.
The license requires manual review.
Шаблон production-style FPGA IP: manifest, registry, board/toolchain scaffolding, SPDX checks, separated licenses and release checklist.
This is a template/example, not a standalone core.
Generated projects require separate review.
| Signal | wb_ram | AccelFury core-template |
|---|---|---|
| Category / source | memory/Wishbone RAM github | generator / template / IP methodology github |
| Review / maturity | Auto indexed M1-M3 candidate | Manually reviewed M2-M3 template |
| License | unknownUnknown | CERN-OHL-S-2.0 + AGPL + CC-BY-SAManual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: NoCI: NoFormal: No | Tests: NoCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: NoFuseSoC: NoBoard demo: No | Docs: YesFuseSoC: NoBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | MemoryWishbone | unknownunknown |
| Toolchains | unknown | Verilator |
| Warnings |
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