wb_ram
M1-M3 candidateMinimal SoC building block.
githubAuto indexedunknown
The license requires manual review.
Comparison helps you see quickly which core carries less license, review, and integration risk.
Minimal SoC building block.
The license requires manual review.
Bus protocol reference for OpenCores-era reusable IP.
Manual review is required.
| Signal | wb_ram | OpenCores Wishbone |
|---|---|---|
| Category / source | memory/Wishbone RAM github | bus/Wishbone opencores |
| Review / maturity | Auto indexed M1-M3 candidate | Auto indexed M6 |
| License | unknownUnknown | public-domain-like per OpenCores WISHBONE pageManual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: NoCI: NoFormal: No | Tests: NoCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: NoFuseSoC: NoBoard demo: No | Docs: YesFuseSoC: NoBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | MemoryWishbone | unknownWishbone |
| Toolchains | unknown | unknown |
| Warnings |
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