YosysHQ sby
M0-M2Formal verification flow signal.
githubAuto indexedunknown
The license requires manual review.
This is not confirmed to be a reusable RTL core.
Comparison helps you see quickly which core carries less license, review, and integration risk.
Formal verification flow signal.
The license requires manual review.
This is not confirmed to be a reusable RTL core.
Central open SoC builder and integration framework.
Manual review is required.
| Signal | YosysHQ sby | LiteX |
|---|---|---|
| Category / source | formal/tooling github | SoC builder/generator github |
| Review / maturity | Auto indexed M0-M2 | Auto indexed M6 |
| License | unknownUnknown | BSD-2-Clause-like until checkedManual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: YesCI: NoFormal: Yes | Tests: NoCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: NoFuseSoC: NoBoard demo: No | Docs: NoFuseSoC: NoBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | unknownunknown | Memoryunknown |
| Toolchains | Yosys | LiteX, Verilator |
| Warnings |
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