YosysHQ sby
M0-M2Formal verification flow signal.
githubAuto indexedunknown
The license requires manual review.
This is not confirmed to be a reusable RTL core.
Comparison helps you see quickly which core carries less license, review, and integration risk.
Formal verification flow signal.
The license requires manual review.
This is not confirmed to be a reusable RTL core.
Useful Wishbone-accessible debug core by ZipCPU author.
Manual review is required.
| Signal | YosysHQ sby | OpenCores WBScope |
|---|---|---|
| Category / source | formal/tooling github | verification/logic analyzer opencores |
| Review / maturity | Auto indexed M0-M2 | Auto indexed M5 candidate |
| License | unknownUnknown | GPLManual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: YesCI: NoFormal: Yes | Tests: NoCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: NoFuseSoC: NoBoard demo: No | Docs: NoFuseSoC: NoBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | unknownunknown | JTAG/debugWishbone |
| Toolchains | Yosys | Verilator |
| Warnings |
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