M_AXI interfaces in AMD Vitis HLS

Name: M_AXI interfaces in AMD Vitis HLS
Start: 2024-11-07
End: 2024-11-07

OnlineCompletedWebinar

FPGA

Connecting HLS-generated hardware to external memory.

Recording

1 found

RecordingAccess not confirmed
Webinar recording
en
Source: webinar.amd.com

Materials checked: Oct 8, 2026

Mark Pettigrew examines cache options, automatic interface widening and bursts. An image-filter example compares coding styles and the array-stencil pragma.

Oct 12 – 15, 2026 United States · San Jose

OCP Global Summit 2026

Open infrastructure sessions and Lattice–AMI demonstrations of platform firmware, management and control technologies.

In person

Oct 16, 2026 Japan · Yokohama

FPGA Development and FPGA AI Suite Hands-on with Agilex 3 and Agilex 5

AI inference with FPGA AI Suite, handwritten-digit recognition on Terasic Atum A3 Nano, and an Agilex 5 demonstration.

In person FPGA

Recording

More events

OCP Global Summit 2026

FPGA Development and FPGA AI Suite Hands-on with Agilex 3 and Agilex 5