MATLAB to AMD Vitis HLS workflow

Name: MATLAB to AMD Vitis HLS workflow
Start: 2025-08-07
End: 2025-08-07

OnlineCompletedWebinar

FPGA

Generating synthesizable C++ with HDL Coder in MATLAB R2025a.

Recording

1 found

RecordingAccess not confirmed
Webinar recording
en
Source: webinar.amd.com

Materials checked: Oct 8, 2026

The session follows algorithm and testbench development through simulation and RTL synthesis. It includes coding guidelines and design examples for AMD FPGAs and adaptive SoCs.

Oct 12 – 15, 2026 United States · San Jose

OCP Global Summit 2026

Open infrastructure sessions and Lattice–AMI demonstrations of platform firmware, management and control technologies.

In person

Oct 16, 2026 Japan · Yokohama

FPGA Development and FPGA AI Suite Hands-on with Agilex 3 and Agilex 5

AI inference with FPGA AI Suite, handwritten-digit recognition on Terasic Atum A3 Nano, and an Agilex 5 demonstration.

In person FPGA

Recording

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