Functional verification of AMD Versal heterogeneous systems

Name: Functional verification of AMD Versal heterogeneous systems
Start: 2026-04-23
End: 2026-04-23

OnlineCompletedWebinar

FPGA

Simulation of AI Engine and programmable-logic designs before hardware implementation.

Recording

1 found

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Webinar recording
en
Source: webinar.amd.com

Materials checked: Oct 8, 2026

The workflow uses MATLAB, Python or C++ and reuses existing testbenches. Hardware-in-the-loop is discussed as a way to debug integration and validate the complete system.

Oct 12 – 15, 2026 United States · San Jose

OCP Global Summit 2026

Open infrastructure sessions and Lattice–AMI demonstrations of platform firmware, management and control technologies.

In person

Oct 16, 2026 Japan · Yokohama

FPGA Development and FPGA AI Suite Hands-on with Agilex 3 and Agilex 5

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Recording

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