Vitis subsystem simulation with hardware-in-the-loop and Python

Name: Vitis subsystem simulation with hardware-in-the-loop and Python
Start: 2026-07-09
End: 2026-07-09

OnlineCompletedWebinar

FPGA

A webinar on combining simulation with hardware execution.

Recording

1 found

RecordingAccess not confirmed
Webinar recording
en
Source: webinar.amd.com

Materials checked: Oct 8, 2026

The flow packages a Vitis Subsystem already checked in software simulation with an HIL server and prepares an SD-card image. Python on the host sends test vectors over Ethernet and captures hardware results.

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