Routing 0.5 mm FPGA packages without HDI

Name: Routing 0.5 mm FPGA packages without HDI
Start: 2026-09-17
End: 2026-09-17

OnlineCompletedWebinar

FPGA

PCB design with FR4 and through-hole vias for AMD Artix UltraScale+.

Recording

1 found

RecordingAccess not confirmed
Webinar recording
en
Source: webinar.amd.com

Materials checked: Oct 8, 2026

AMD and Adiuvo use the AU7P-based Explorer Board to explain offset through-hole via routing. The page labels the recording as 90 minutes; board prices and measured interface performance are vendor statements.

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